In recent years, there have been great advancements in the speed, power, and complexity of integrated circuits (ICs), such as application specific integrated circuit (ASIC) chips, radio frequency integrated circuits (RFIC), central processing unit (CPU) chips, digital signal processor (DSP) chips and the like. These advancements have made possible the development of system-on-a-chip (SOC) devices, among other things. A SOC device integrates into a single chip all (or nearly all) of the components of a complex electronic system, such as a wireless receiver (i.e., cell phone, a television receiver, microprocessor, high-speed data transceiver, and the like).
In many integrated circuits, the clock signals that drive an integrated circuit are generated by a frequency synthesizer phase-locked loop (PLL) or a delay locked loop (DLL). PLLs and DLLs are well known to those skilled in the art and have been extensively written about. The dynamic performance of the frequency synthesizer that is used to generated clock signals is dependent on several parameters, including the natural frequency (Fn), the damping factor (DF), the crossover frequency (F0) and the ratio of the comparison frequency (Fc) to the crossover frequency. The first three parameters depend on the voltage controlled oscillator (VCO) gain (K0), the F/B (N) divider value, the charge pump current (Ic), and the loop filter components.
The last parameter (i.e., the ratio of comparison frequency to crossover frequency) is dependent on the input divider (M) value, as well as the frequency of the input clock itself.
The performance of the frequency synthesizer is also is dependent on the performance of the charge pump located in the PLL or DLL. The charge pump pulse timing jitter and pulse amplitude noise both contribute to synthesizer phase noise. A typical charge pump includes circuitry to avoid what is known as the “dead zone.” The dead zone occurs at or near the PLL “lock” state when the phase error is very small and the loop gain would otherwise approach zero. To avoid this problem, both the Pump Up current source and the Pump Down current source of a charge pump are turned ON simultaneously for a brief period at the end of each phase detector cycle. However, to reduce charge pump output noise, it is desirable to reduce the ON time of the charge pump output in the “lock” state.
As the simultaneous ON time is reduced, the goal is to balance the injected charge from the Pump Up current source and the Pump Down current source so that a periodic glitch caused by charge imbalance is not injected into the loop filter, thereby causing frequency spurs on the VCO output. This is difficult to do because the transistor devices used in the Pump Up and Pump Down current sources are different channel type devices with different parasitic characteristics. The problem is further exacerbated when the ON time is reduced to lower the phase noise contribution of the charge pump.
Therefore, there is a need in the art for improved frequency synthesizers for use in generating reference frequency signals. In particular, there is a need in the art for improved charge pumps for use in phase-locked loops or delay-locked loops. More particularly, there is a need for charge pumps that minimize the charge current imbalances in lock state.